1. Field of the Invention
The present invention relates to a device for testing semiconductor elements, especially to a device for testing electrical characteristics of a chip.
2. Description of the Related Art
As for the increasing requirement for the portability of consumer electronic products, the flip-chip technology definitely provides the best method to achieve the object of making electrical products lighter, thinner, shorter and smaller. For this technology, it is a very important issue about how to increase the stability and reliability of the electrical characteristics of the bumps. If the bumps have bad connections, the electrical performances and the lifetime of the consumer electronic products will be impacted.
After the completion of the front-end wafer manufacturing process and before the back-end package process, the electrical characteristics of each chip 12 have to be tested on the wafer 11 first, as shown in FIG. 1. If there are defects found in the electrical characteristics of the chip 12, they will be marked on the surface of the chip 12 and, after the wafer 11 is diced, the defected chip 12 will be rejected or employed in other downgrade applications.
Generally speaking, in flip-chip technology, there are many bumps 23 provided on the chip 12 to serve as the electrical connections of the chip 12 with the external circuit board or with the other chip, as shown in FIG. 2. There is an under bump metallurgy (UBM) 24 provided between the bump 23 and the bonding pad 21 of the chip 12, which typically includes three metal layers (for example, wetting layer 241, barrier layer 242 and adhesion layer 243) laminated above bonding pad 21 in sequence as shown in the table below:
NameAdhesion layerBarrier layerWetting layerType  Material243242241Al bonding padAlNi—VCuCu bonding padTiNi—VCuCrNi—VCuThicknessHundreds of A°0.5˜1.0 μmHundreds of A°PurposeFirmly adhere toProtect theWeld with thethe protectioncircuit layerbump materiallayer and theagainstbonding padpenetration ofthe bumpmaterial
There is a protection layer 22 (or named passive layer) provided on the lateral of the interface between the UBM 24 and the bonding pad 21. The purpose of the UBM 24 described in the above table has an area that is slightly smaller than or approximately equal to the cross-sectional area of the bump 23.
When the electrical characteristics of the chip 12 are conventionally tested, a probe 31 is used to contact the bumps 23 of each chip 12 directly respectively, as shown in FIG. 3(a). The material of the bump 23 can be selected from gold or solder etc., and can be bumped by the electroplating, deposition or printing on the bonding pad 21 of the chip 12 so as to transmit the electrical signal with the substrate 33 or the other chips. The signal detected by the probe 31 is verified by a testing program of a testing machine (not shown).
However, the conventional test method often results in many problems, referring to FIGS. 3(a) to 3(d). During the testing process, the probe 31 downwards contacts and presses on the bump 23, such that a recess 32 is easily formed at the contact area of the bump 23, as shown in FIG. 3(b). Thereafter, while the chip 12 and the substrate 33 proceed with a reflow process, it is extremely liable to cause the welded bump 35 to have voids or bubbles 34, resulting in weak electrical connection or function failure. Even the chip 12 may pass the electrical testing criteria; it would prematurely fail in the succeeding operation caused by inferior reliability.